Band-gap reference (BGR) circuits provide stable reference voltages that vary little with process, supply-voltage, and temperature (PVT). Many circuits—including dynamic random-access memories, flash memories, and analog devices—employ BGR circuits.
The band-gap voltage Vbg of conventional BGR circuits is typically about 1.25 volts. Modern integrated circuits, however, are using ever-lower supply voltages, putting downward pressure on the output voltage of BGR circuits. Some modern devices, for example, employ 1.2-volt power supplies (e.g., Vdd is 1.2 volts), making it impractical to derive a 1.25-volt BGR voltage. Researchers have therefore directed their attention to the creation of BGR circuits with reduced band-gap voltage levels. For a more detailed discussion of BGR circuits, see U.S. Pat. No. 6,489,835 to Yu et al. and U.S. Pat. No. 6,323,630 to Banba, both of which are incorporated herein by reference.
FIG. 1A (prior art) depicts a BGR circuit 100 capable of producing a stable BGR voltage with supply voltages below one volt. A differential amplifier Dal receives a pair of input voltages Va and Vb. Input voltage va is derived, in part, from the forward voltage Vf1 of a diode D1, while input voltage Vb is derived, in part, from the forward voltage Vf2 of a collection of N diodes D2. The output from differential amplifier Dal provides the requisite gate bias for PMOS transistors P1, P2, and P3 to maintain the equivalence of input voltages Va and Vb (i.e., Va=Vb). PMOS transistors P1, P2, and P3 are identical and have the same bias voltages, so their respective currents I1, I2, and I3 are equal (i.e., I1=I2=I3).
The input terminals of differential amplifier Da1 connect to the drains of respective transistors P1 and P2 via respective voltage dividers R4 (resistors R4a and R4b) and R2 (resistors R2a and R2b). Assuming R2a=R4a and R2b=R4b gives:I1a=I2aI1b=I2bVa=Vf1[R4b/(R4a+R4b)]Vb=Vf2+dvf[R2b/(R2a+R2b)]dVf=Vf1−Vf2Because the voltage across R1 is dVf, this gives:I2a=dVf/R1I2b=Vf1/(R2a+R2b)Thus, I2=I2a+I2b=[Vf1/(R2a+R2b)]+dvf/R1
Vref =R3*I3=R3*I2=R3{[Vf1/(R2a+R2b)] + (dVf/R1)}=[R3/(R2a+R2b)] * {Vf1+[dVf(R2a+R2b)/R1]}
The resistance ratio (R2a+R2b)/R1 can be set so that vref is not temperature dependent, and the resistance ratio R3/(R2a+R2b) can be used to adjust the Vref level within the range of the power supply. Voltage dividers R4 and R2 reduce voltages Va and Vb below Vf1, which may be advantageous for very low Vdd levels. The ratio between R2a and R2b (and similarly between R4a and R4b) is optimized for a given application. BGR circuit 100 is discussed in more detail in the above-referenced Banba patent.
FIG. 1B is waveform diagram 150 approximating a pair of simulated responses of BGR circuit 100 to the application of a 1.8-volt supply voltage Vdd. (As with other designations in the present disclosure, Vdd refers to both the signal and the corresponding signal node. Whether a given designation refers to a signal or a node will be clear from the context.)
Diagram 150 includes two response curves: a first curve 160 depicts the response of BGR signal Vbg to the application of supply voltage Vdd at a first temperature, and a second curve 165 depicts the response of BGR signal Vbg to the application of the same supply voltage Vdd at a second, lower temperature. The slower response of curve 165 indicates that the response of BGR circuit 100 shifts later in time with reduced temperatures. This shift occurs because the forward voltages vf of diodes D1 and D2 increase with reduced temperature, so Vdd must rise higher before diodes D1 and D2 conduct.
Typical integrated circuits (ICs) function over a range of power-supply voltages, and can be expected to fail if operating with supply voltage outside this range. ICs therefore commonly include a so-called “Power-On-Reset” (POR) circuit that resets the IC to a known state upon application of power and holds the known state until the power supply voltages settle at or near some predetermined level. Typically, the POR circuit is powered by the same source as the rest of the IC.
FIG. 2A depicts a conventional POR circuit 200, which includes a BGR circuit 200, a voltage comparator 210 (a differential amplifier), and a voltage divider 215 connected between supply voltage Vdd and ground. BGR 205 provides a BGR signal Vbg to the non-inverting input of comparator 210; voltage divider 215 provides a reference voltage Va, a fraction of supply voltage Vdd, to the inverting input of comparator 210. Comparator 210 compares band-gap voltage Vbg and reference voltage Va to generate a POR signal.
FIG. 2B is a waveform diagram 220 depicting the response of POR circuit 200 to power applied to supply terminals vdd and ground, at time zero, to produce a rising potential difference between vdd and ground. For illustrative purposes, supply voltage Vdd is assumed to rise linearly from zero to 1.8 volts over a power-up time of about 300 microseconds (line 225). BGR circuit 205 can be any of many such circuits, but is assumed to be like BGR circuit 100 for this illustration. Response curves 160 and 165 of BGR circuit 100 are therefore included in FIG. 2B.
Reference voltage Va is merely a divided version of supply voltage Vdd, and thus increases linearly in proportion to Vdd as Vdd ramps up from zero to 1.8 volts. In contrast, BGR signal Vbg ramps up in a non-linear fashion due to the non-linear components (diodes and transistors) employed to generate BGR signal Vbg. The level of BGR signal Vbg can therefore cross the level of reference voltage Va a number of times, producing one or more undesirable “windows” W in the POR signal. In this example, the low-temperature Vbg curve 165 produces a troublesome window, but the higher temperature Vbg curve 160 does not. The relationship between reference voltage va and curves 160 and 165 illustrate that POR circuits are especially susceptible to producing windows when operating at extreme values of process, temperature, and voltage. If such windows are unavoidable, it is preferred that they disappear early and at a relatively low vdd value.